`timescale 1ns / 1ps

module graycode_sim();
    reg rst_n = 1'b1;
    reg clk = 1'b0;
    reg en = 1'b1;
    wire [3:0] gray;

    graycode UUT(
        .rst_n_i(rst_n),
        .clk_i(clk),
        .en_i(en), 
        .gray_o(gray)
        );
    
    always #2 begin clk = ~clk; end
    
    initial begin
        // initial: normal output
        #21 en = 1'b0;  // DISABLE OUTPUT
        #10 en = 1'b1;  // ENABLE OUTPUT
        #20 rst_n = 1'b0;  // ASYNC SETZ
        #10 rst_n = 1'b1;  // back to normal
        #20 $stop;
    end
endmodule
